Back-biased face target sputtering based high density non-volatile caching data storage

ABSTRACT

Systems and methods are disclosed for forming stacked substrates with data storage arrays formed on each substrate in an air-tight chamber in which an inert gas is admittable and exhaustible; a pair of target plates placed at opposite ends of said air-tight chamber respectively so as to face each other and form a plasma region therebetween; a pair of magnets respectively disposed adjacent to said target plates such that magnet poles of different polarities face each other across said plasma region thereby to establish a magnetic field of said plasma region between said target plates; a substrate holder disposed adjacent to said plasma region, said substrate holder adapted to hold a substrate on which an alloyed thin film is to be deposited; and a back-bias power supply coupled to the substrate holder wherein data is selectively stored in a disk drive or the nonvolatile data storage arrays depending on an update ratio of the data.

BACKGROUND

This Application is a continuation-in-part of to Ser. No. 11/252,278,the content of which is incorporated by reference.

The present invention relates to systems and methods for fabricatingsemiconductor devices at low temperature.

Electronic systems have become a ubiquitous fixture in modern society.These electronic systems range from simple, hand-held calculators tomore complex systems including computers, personal digital assistants(PDAs), embedded controllers and complex satellite imaging andcommunications systems. As noted in U.S. Pat. No. 6,862,211, manyelectronic systems include a microprocessor that performs one or morefunctions based on data provided to the microprocessor. This data istypically stored in a memory device of the electronic system such as acommon dynamic random access memory (DRAM) device. A DRAM typicallyincludes an array of memory cells that store data as binary values,e.g., 1's and 0's. The DRAM data is stored by controlling the charge oncapacitors in each cell of the DRAM. Data in the array is “randomlyaccessible” since a processor can retrieve data from any location inmemory by providing the appropriate address to the memory device. Oneproblem with conventional DRAM is that the device is “volatile.” Thismeans that when power is turned off to the system using the DRAM, thedata in the memory device is lost.

To increase capacity, U.S. Pat. No. 5,229,647 discloses a solid-statememory unit constructed using stacked wafers containing a large numberof memory units in each wafer. Vertical connections between wafers arecreated using bumps at the contact points and metal in through-holesaligned with the bumps. The bumps on one wafer make contact with metalpads on a mating wafer. Mechanical bonding between the bumps and matingmetal pads on another wafer is preferably avoided so that fractures dueto thermal expansion differentials will be prevented. Serial addressingand data access is employed for the memory units to minimize the numberof connections needed. Also, the metal pads, through-holes and bumps areformed at corners of the die and thus shared with adjacent unitswhenever possible, further reducing the number of vertical connections.

In a parallel trend, various semiconductor fabrication steps need to bedone at low temperature. For instance, when applying a ferroelectricthin film to a highly integrated device, conventional processes do notprovide a ferroelectric thin film which sufficiently fulfills variousconditions, such as denseness and evenness on the thin film surfacerequired for fine processing and formation of film at a relatively lowtemperature.

U.S. Pat. No. 5,000,834 discloses a vacuum deposition technique known asface target sputtering to form thin films on magnetic recording heads atlow temperature. The sputtering method is widely used for forming a thinfilm on a substrate made of PMMA because of intimacy between thesubstrate and the thin film formed therethrough. The amorphous thin filmof rare earth—transition metal alloy formed through the sputteringmethod is applied to an erasable magneto-optical recording medium. Thesputtering method is performed as follows: Positive ions of an inert gassuch as Argon (Ar) first created by a glow discharge are acceleratedtoward a cathode or target, and then they impinge upon the target. As aresult of ionic bombardment, neutral atoms and ions are removed from thetarget surface into a vacuum chamber due to the exchange of momentumtherebetween. The liberated or sputtered atoms and ions are consequentlydeposited on a preselected substrate disposed in the vacuum chamber.

U.S. Pat. No. 6,156,172 discloses a plasma generating unit and a compactconfiguration of the combination of plasma space and substrate holdersfor a facing target type sputtering apparatus which includes: anarrangement for defining box-type plasma units supplied therein withsputtering gas mounted on outside wall-plates of a closed vacuum vessel;at least a pair of targets arranged to be spaced apart from and face oneanother within the box-type plasma unit, with each of the targets havinga sputtering surface thereof; a framework for holding five planes of thetargets or a pair of facing targets and three plate-like membersproviding the box-type plasma unit so as to define a predetermined spaceapart from the pair of facing targets and the plate-like members, whichframework is capable of being removably mounted on the outside walls ofthe vacuum vessel with vacuum seals; a holder for the target havingconduits for a coolant; an electric power source for the targets tocause sputtering from the surfaces of the targets; permanent magnetsarranged around each of the pair of targets for generating at least aperpendicular magnetic field extending in a direction perpendicular tothe sputtering surfaces of the facing targets; devices for containingthe permanent magnets with target holders, removably mounted on theframework; and a substrate holder at a position adjacent the outletspace of the sputtering plasma unit in the vacuum vessel. The unifiedconfiguration composed of a cooling device for cooling both the backsideplane of the targets and a container of magnets in connection with theframework improves the compactness of sputtering apparatus.

SUMMARY

In one aspect, systems and methods are disclosed for forming stackedsubstrates with data storage arrays formed on each substrate in anair-tight chamber in which an inert gas is admittable and exhaustible; apair of target plates placed at opposite ends of said air-tight chamberrespectively so as to face each other and form a plasma regiontherebetween; a pair of magnets respectively disposed adjacent to saidtarget plates such that magnet poles of different polarities face eachother across said plasma region thereby to establish a magnetic field ofsaid plasma region between said target plates; a substrate holderdisposed adjacent to said plasma region, said substrate holder adaptedto hold a substrate on which an alloyed thin film is to be deposited;and a back-bias power supply coupled to the substrate holder, whereindata is selectively stored in a hard disk drive or cached in thenonvolatile data storage device depending on an update ratio of thedata.

Implementations of the above systems can include one or more of thefollowing. The stacked substrates are electrically interconnected andcan be accessed through row/column decoders as well as substrate selectsignals.

A memory tester can characterize the data storage devices. Wire-bondingequipment can electrically connect the substrates. The data storagedevices comprise row and column decoders as well as address input and adata input/output.

In another aspect, a data storage system contains a plurality of wafersmade from a back-biased fabrication machine. The wafers are arranged ina stack; each wafer having a plurality of non-volatile data storagedevices formed thereon and each wafer being electrically coupled to anadjacent wafer. A housing is provided to protect the wafers.

In implementations, each wafer has a plurality of connection pads. Eachwafer can have a plurality through-holes axially aligned with theconnection pads, each through-hole extending through the wafer to anopposite face of the wafer. Each wafer can have a plurality of solidbumps of a second metallic material, each bump engaging and makingelectrical contact with a connection pad formed on the wafer at aninterface and extending through the through-hole of another wafer tomake electrical contact with a connection pad formed on the adjacentwafer. The housing can have springs or suitable shock absorber toprotect the stacked wafers.

The system provides a low-cost solid state data device construction,particularly a memory system using wafer scale integration of memoryunits. The memory units are interconnected within a wafer, and thewafers are interconnected in a stacked wafer construction of a memorysystem. The system also provides an improved data storage systememploying flash data storage in a stacked wafer arrangement. Thevertical interconnections in a stacked wafer semiconductor device resultin high density storage at a relatively low cost.

In another aspect, a method for sputtering a thin film onto a substrateincludes providing at least one target and a substrate having afilm-forming surface portion and a back portion; creating a magneticfield so that the film-forming surface portion is placed in the magneticfield with the magnetic field induced normal to the substrate surfaceportion; back-biasing the back portion of the substrate; and sputteringmaterial onto the film-forming surface portion.

Advantages of the invention may include one or more of the following.The substrate temperature in forming a thin film is approximately thatof room temperature, and the process requires a short time. Since thethin film is formed at a very low temperature during substantially thewhole process, the process can be applied to a highly integrated deviceto deposit an additional layer with a plurality of elements withoutdamaging other elements previously deposited using conventionaldeposition.

BRIEF DESCRIPTION OF THE FIGURES

In order that the manner in which the above-recited and other advantagesand features of the invention are obtained, a more particulardescription of the invention briefly described above will be rendered byreference to specific embodiments thereof, which are illustrated, in theappended drawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be considered tobe limiting of its scope, the invention will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings in which:

FIG. 1 shows one embodiment of an apparatus for fabricatingsemiconductor.

FIG. 2 is an exemplary electron distribution chart.

FIG. 3 shows one embodiment of an FTS unit.

FIG. 4A shows one embodiment of a second apparatus for fabricatingsemiconductor.

FIG. 4B shows one embodiment of a second apparatus for fabricatingsemiconductor.

FIG. 5 shows an SEM image of a cross sectional view of an exemplarydevice fabricated with the system of FIG. 1.

FIG. 6 is an enlarged view of one portion of the SEM image of FIG. 5.

FIG. 7 shows an exemplary memory array made using the system of FIG. 1.

FIG. 8 shows an exemplary FPGA configuration memory made using thesystem of FIG. 1.

FIG. 9 shows an exemplary stacked array of substrates made using thesystem of FIG. 1.

FIG. 10 shows an exemplary non-volatile data storage array used as adisk cache to enhance overall computer system performance.

DESCRIPTION

Referring now to the drawings in greater detail, there is illustratedtherein structure diagrams for a semiconductor processing system andlogic flow diagrams for processes a system will utilize to deposit amemory device at low temperature, as will be more readily understoodfrom a study of the diagrams.

FIG. 1 shows one embodiment of an apparatus for fabricatingsemiconductor. An embodiment reactor 10 is schematically illustrated inFIG. 1. The reactor 10 includes a metal chamber 14 that is electricallygrounded. A wafer or substrate 22 to be sputter coated is supported on apedestal electrode 24 in opposition to the target 16. An electrical biassource 26 is connected to the pedestal electrode 24. Preferably, thebias source 26 is an RF bias source coupled to the pedestal electrode 24through an isolation capacitor. Such bias source produces a negative DCself-bias VB on the pedestal electrode 24 on the order of tens of volts.A working gas such as argon is supplied from a gas source 28 through amass flow controller 30 and thence through a gas inlet 32 into thechamber. A vacuum pump system 34 pumps the chamber through a pumpingport 36.

An FTS unit is positioned to face the wafer 22 and has a plurality ofmagnets 102, 104, 106, and 108. A first target 110 is positioned betweenmagnets 102 and 104, while a second target 120 is positioned betweenmagnets 106 and 108. The first and second targets 110 and 120 define anelectron confining region 130. A power supply 140 is connected to themagnets 102-108 and targets 110-120 so that positive charges areattracted to the second target 120. During operation, particles aresputtered onto a substrate 22 which, in one embodiment where the targets110 and 120 are laterally positioned, is vertically positioned relativeto the lateral targets 110 and 120. The substrate 22 is arranged to beperpendicular to the planes of the targets 110 and 120. A substrateholder 24 supports the substrate 22.

The targets 110 and 120 are positioned in the reactor 10 in such amanner that two rectangular shape cathode targets face each other so asto define the plasma confining region 130 therebetween. Magnetic fieldsare then generated to cover vertically the outside of the space betweenfacing target planes by the arrangement of magnets installed in touchwith the backside planes of facing targets 110 and 120. The facingtargets 110 and 120 are used as a cathode, and the shield plates areused as an anode, and the cathode/anode are connected to outputterminals of the direct current (DC) power supply 140. The vacuum vesseland the shield plates are also connected to the anode.

Under pressure, sputtering plasma is formed in the space 130 between thefacing targets 110 and 120 while power from the power source is applied.Since magnetic fields are generated around the peripheral area extendingin a direction perpendicular to the surfaces of facing targets 110 and120, highly energized electrons sputtered from surfaces of the facingtargets 110 and 120 are confined in the space between facing targets 110and 120 to cause increased ionized gases by collision in the space 130.The ionization rate of the sputtering gases corresponds to thedeposition rate of thin films on the substrate 22, then, high ratedeposition is realized due to the confinement of electrons in the space130 between the facing targets. The substrate 22 is arranged so as to beisolated from the plasma space between the facing targets 110 and 120.

Film deposition on the substrate 22 is processed at a low temperaturerange due to a very small number of impingement of plasma from theplasma space and small amount of thermal radiation from the targetplanes. A typical facing target type of sputtering method has superiorproperties of depositing ferromagnetic materials at high rate depositionand low substrate temperature in comparison with a magnetron sputteringmethod. When sufficient target voltage VT is applied, plasma is excitedfrom the argon. The chamber enclosure is grounded. The RF power supply26 to the chuck or pedestal 24 causes an effective D/C ‘back-bias’between the wafer and the chamber. This bias is negative, so it repelsthe low-velocity electrons.

FIG. 2 illustrates an exemplary electron distribution for the apparatusof FIG. 1. The electron distribution follows a standard Maxwelliancurve. Low energy electrons have two characteristics: they are numerousand they tend to have non-elastic collisions with the deposited atoms,resulting in amorphization during deposition. High-energy electrons comethrough the back-biased shield, but they effectively “bounce” off theatoms without significant energy transfer—these electrons do not affectthe way bonds are formed. This is especially true because high energyelectrons spend very little time in the vicinity of the atoms, while thelow energy electrons spend more time next to the atoms and can interferewith bond formation.

The presence of the large positively biased shield affects the plasma,particularly those close to the pedestal electrode 24. As a result, theDC self-bias developed on the pedestal 24, particularly by an RF biassource, may be more positive than for the conventional large groundedshield, that is, less negative since the DC self-bias is negative intypical applications. It is believed that the change in DC self-biasarises from the fact that the positively biased shield drains electronsfrom the plasma, thereby causing the plasma and hence the pedestalelectrode to become more positive.

FIG. 3 shows another embodiment of an FTS system. In this embodiment, awafer 200 is positioned in a chamber 210. The wafer 200 is moved intothe chamber 210 using a robot arm 220. The robot arm 220 places thewafer 200 on a wafer chuck 230. The wafer chuck 230 is moved by a chuckmotor 240. One or more chuck heaters 250 heats the wafer 200 duringprocessing.

Additionally, the wafer 200 is positioned between the heater 250 and amagnetron 260. The magnetron 260 serves as highly efficient sources ofmicrowave energy. In one embodiment, microwave magnetrons employ aconstant magnetic field to produce a rotating electron space charge. Thespace charge interacts with a plurality of microwave resonant cavitiesto generate microwave radiation. One electrical node 270 is provided toa back-bias generator such as the generator 26 of FIG. 1.

In the system of FIG. 3, two target plates are respectively connectedand disposed onto two target holders which are fixed to both inner endsof the chamber 210 so as to make the target plates face each other. Apair of permanent magnets are accommodated in the target holders so asto create a magnetic field therebetween substantially perpendicular tothe surface of the target plates. The wafer 200 is disposed closely tothe magnetic field (which will define a plasma region) so as topreferably face it. The electrons emitted from the both target plates byapplying the voltage are confined between the target plates because ofthe magnetic field to promote the ionization of the inert gas so as toform a plasma region. The positive ions of the inert gas existing in theplasma region are accelerated toward the target plates. The bombardmentof the target plates by the accelerated particles of the inert gas andions thereof causes atoms of the material forming the plates to beemitted. The wafer 200 on which the thin film is to be disposed isplaced around the plasma region, so that the bombardment of these highenergy particles and ions against the thin film plane is avoided becauseof effective confinement of the plasma region by the magnetic field. Theback-bias RF power supply causes an effective DC ‘back-bias’ between thewafer 200 and the chamber 210. This bias is negative, so it repels thelow-velocity electrons.

FIG. 4A shows one embodiment of a second apparatus for fabricatingsemiconductor. In the system of FIG. 4A, multiple 1-D deposition sourcesare stacked in the deposition chamber. The stacking of the sourcesreduces the amount of wafer travel, while significantly increasingdeposition uniformity. A wafer 300 is inserted into a chamber 410 usinga robot arm 420 moving through a transfer chamber 430. The wafer 300 ispositioned onto a rotary chuck 440 with chuck heater(s) 450 positionedabove the wafer. A linear motor 460 moves the chuck through a pluralityof deposition chambers 470.

The system of FIG. 4A provides a plurality of one dimensional sputterdeposition chambers. Each chamber can deposit a line of material. Bymoving the wafer 300 with the linear motor 460, 2-d coverage isobtained.

Turning now to FIG. 4B, a second embodiment of a fabrication apparatusis shown. In this embodiment, a chuck 500 is positioned inside achamber. The chuck 500 supports a wafer 502. The chamber has vacuumbellows 510. The chuck 500 is driven by a wafer rotator 520 whichrotates the wafer 502 and the chuck 500 in a pendulum-like manner. Thechuck 500 is also powered by a linear motor 530 to provide up/downmotion. A plurality of sources 540-544 perform deposition of materialson the wafer 502.

The system of FIG. 4B gets linear motion of the wafer 502 past the threesources for uniform deposition. This is done through a chuck supportedfrom underneath rather than from the side. A jointed pendulum supportsthe wafer and keeps the wafer at a constant vertical distance from thetarget as the pendulum swings. The system swings the wafer using apendulum. The system is more stable than a system with a lateral lineararm since the chuck 500 is heavy and supports the weight of the wafer, aheater, and RF back-bias circuitry and would require a very thicksupport arm otherwise the arm would wobble. Also, the linear arm wouldneed to extend away from the source, resulting in large equipment. Inthis implementation, the arm sits below the chuck, resulting in asmaller piece of equipment and also the arm does not have to supportmuch weight.

In one embodiment, a process for obtain 2D deposition coverage is asfollows:

Receive desired 2D pattern from user

Move chuck into a selected deposition chamber;

Actuate linear motor and rotary chuck to in accordance with the 2Dpattern

Move current wafer to next deposition chamber

Get next wafer into the current chamber and repeat process.

FIG. 5 shows an SEM image of an exemplary device fabricated with thesystem of FIG. 1, while FIG. 6 is an enlarged view of one portion of theSEM image of FIG. 5. The device of FIG. 5 was fabricated at a lowtemperature (below 400° C.). At the bottom of FIG. 5 is an oxide layer(20 nm thick). Above the oxide layer is a metal layer, in this case atitanium layer (24 nm thick). Above this layer is an interface layer, inthis case a platinum (Pt) interface face layer (about 5 nm). Finally, acrystallite PCMO layer (79 nm thick) is formed at the top. Grains inthis layer can be seen extending from the bottom toward the top with aslightly angled tilt. FIG. 6 shows a zoomed view showing the Ti metallayer, the Pt interface layer and the PCMO grain in more details.

Although one back-biased power supply is mentioned, a plurality ofback-bias power supplies can be used. These power supplies can becontrollable independently from each other. The electric energiessupplied can be independently controlled. Therefore, the components ofthe thin film to be formed are easily controlled in every sputteringbatch process. In addition, the composition of the thin film can bechanged in the direction of the thickness of the film by using theFacing Targets Sputtering device.

One or more electronic devices can be formed on the wafer. The devicecan be non-volatile memory such as magneto-resistive random accessmemory (MRAM). Unlike conventional DRAM, which uses electrical cells(e.g., capacitors) to store data, MRAM uses magnetic cells. Becausemagnetic memory cells maintain their state even when power is removed,MRAM possesses a distinct advantage over electrical cells.

In one embodiment, the MRAMs formed using the above FTS has two smallmagnetic layers separated by a thin insulating layer typically make upeach memory cell, forming a tiny magnetic “sandwich.” Each magneticlayer behaves like a tiny bar magnet, with a north pole and south pole,called a magnetic “moment.” The moments of the two magnetic layers canbe aligned either parallel (north poles pointing in the same direction)or antiparallel (north poles pointing in opposite directions) to eachother. These two states correspond to the binary states—the 1's and0's—of the memory. The memory writing process aligns the magneticmoments, while the memory reading process detects the alignment. Data isread from a memory cell by determining the orientation of the magneticmoments in the two layers of magnetic material in the cell. Passing asmall electric current directly through the memory cell accomplishesthis: when the moments are parallel, the resistance of the memory cellis smaller than when the moments are not parallel. Even though there isan insulating layer between the magnetic layers, the insulating layer isso thin that electrons can “tunnel” through the insulating layer fromone magnetic layer to the other.

To write to an MRAM cell, currents pass through wires close to (but notconnected to) the magnetic cell. Because any current through a wiregenerates a magnetic field, this field can change the direction of themagnetic moment of the magnetic material in the magnetic cell. Thearrangement of the wires and cells is called a cross-point architecture:the magnetic junctions are set up along the intersection points of agrid. Word lines run in parallel on one side of the magnetic cells. Bitlines runs on a side of the magnetic cells opposite the word lines. Thebit lines are perpendicular to the set of word lines below. Likecoordinates on a map, choosing one particular word line and oneparticular bit line uniquely specifies one of the memory cells. To writeto a particular cell (bit), a current is passed through the word lineand bit line that intersect at that particular cell. Only the cell atthe crosspoint of the word line and the bit line sees the magneticfields from both currents and changes state.

In one exemplary memory cell array shown in FIG. 7, word lines forselecting rows and bit lines for selecting columns are arranged tointersect at right angles. Memory cells are formed at intersections, anda peripheral driver circuit for selectively allowing information to bewritten into or read from the memory cells and an amplifier circuitwhich for reading the information are also formed. The peripheralcircuit section includes a word line driver circuit and bit line drivercircuit and a signal detecting circuit such as a sense amplifier, forexample.

In another embodiment, the memory can be used in Programmable logicdevices (PLDs) as well. PLDs can implement user-defined logic functionsby interconnecting user-configurable logic cells through a variety ofsemiconductor switching elements. The switching elements may beprogrammable elements such as fuses or antifuses which can be programmedto respectively connect or disconnect logical circuits. As it is wellknown, a fuse is a device having two electrodes and a conductive elementwhich electrically connects the two electrodes. When a fuse isprogrammed, by passage of sufficient current between its electrodes, thetwo electrodes are electrically disconnected. By contrast, an antifuseis a structure, having two electrodes, which are not electricallyconnected when unprogrammed. However, when programmed the first andsecond electrodes of the antifuse are permanently electricallyconnected. An antifuse can be programmed by applying sufficient voltage(“programming voltage”) between its first and second electrodes, therebyforming a bi-directional conductive link between the first and thesecond electrodes.

The configuration relating to the programming of the fuses or antifusescan be stored in the memory cells in one embodiment. FIG. 8 shows memorycells holding configuration data for an FPGA chip. The memory cells ofFIG. 8 are made using the back-biased FTS technique as discussed above.A frame shift register 61 receives a bitstream and loads the array ofmemory cells. Address shift register 62 selects which column of memorycells is loaded from frame shift register 61. Selection of the column ismade by shifting a token logical 1 through word line register 62. In theillustration of FIG. 8, the leftmost column holds the logical 1. Thuswhen frame shift register 61 is filled with a frame of bitstream data,and word line 12 is high the data bit in memory cell M-61 of shiftregister 61, is applied to bit line 11 and loaded into memory cell M41.Other memory cells are equivalently loaded.

In yet another embodiment, a separate memory array can be providedtogether with the FPGA configuration memory to allow a configured FPGAdevice to access the memory array as a buffer, for example.

It is to be understood that various terms employed in the descriptionherein are interchangeable. Accordingly, the above description of theinvention is illustrative and not limiting. Further modifications willbe apparent to one of ordinary skill in the art in light of thisdisclosure.

The invention has been described in terms of specific examples which areillustrative only and are not to be construed as limiting. The inventionmay be implemented in digital electronic circuitry or in computerhardware, firmware, software, or in combinations of them.

Apparatus of the invention for controlling the fabrication equipment maybe implemented in a computer program product tangibly embodied in amachine-readable storage device for execution by a computer processor;and method steps of the invention may be performed by a computerprocessor executing a program to perform functions of the invention byoperating on input data and generating output. Suitable processorsinclude, by way of example, both general and special purposemicroprocessors. Storage devices suitable for tangibly embodyingcomputer program instructions include all forms of non-volatile memoryincluding, but not limited to: semiconductor memory devices such asEPROM, EEPROM, and flash devices; magnetic disks (fixed, floppy, andremovable); other magnetic media such as tape; optical media such asCD-ROM disks; and magneto-optic devices. Any of the foregoing may besupplemented by, or incorporated in, specially-designedapplication-specific integrated circuits (ASICs) or suitably programmedfield programmable gate arrays (FPGAs).

Turning now to FIG. 9, an exemplary high capacity non-volatile datastorage system is shown. A number of the wafers 610 are mounted in astack on a printed circuit board 617, within an enclosure 618hermetically sealed to the printed circuit board. Other components 619such as a gate array and FPGA for data storage control and ECC functionsare also mounted on the printed circuit board 617 to provide a completememory system in a size and form factor for mounting in a standardPCMCIA card, SDIO card, expansion board slot or in a disk bay of adesktop computer or workstation.

First, the memory wafers are fabricated using the back-biasedfabrication techniques as described above. The memory wafers are tested,resulting in “known good”, fully tested and guaranteed by themanufacturer. In one embodiment, the wafers are protected by a thinglass layer with exposed solder bump terminals and then are stackedabove a die cap. The die cap can be a block of either aluminum nitrideor ceramic material which has been manufactured to allow the mounting ofsolder bumped die onto its mounting surface to pads which are connectedto metallized castellations around the periphery of the die cap. Thisconstruction allows the use of existing electronic packaging materialsand technologies to adapt the die stack with test sockets and surfacemounting equipment.

In another embodiment, the semiconductor wafers are processed normallyup through the step of metallization and patterning to form the metalpads, then applying a passivation (oxide or nitride) layer on the topface of the wafers and patterning to expose the pads. Through-holes arethen etched from the backside of the wafers, using a wet-etch orreactive ion etch, stopping on the diffused regions. That is, in such amethod, the through-hole does not extend all the way through the wafer.In another embodiment, an etch is used that stops on metal, in whichcase the holes go all the way through to the underside of the metalpads. A protective insulator layer is then applied, as by depositingsilicon oxide or silicon nitride, and a thin metal coating is applied byevaporation or sputtering then patterned by photoresist mask and etch todefine the area of the bumps. The material of the bumps is deposited byplating on the metal, for example, to fill the through-holes and buildup to the desired uniform height. A photoresist mask is used to definethe bumps during this plating operation.

In another embodiment, memory chips which tested good in a wafer areinterconnected with additional discrete wiring. The system provides alow-cost solid state data device construction, particularly a memorysystem using wafer scale integration of memory units. The memory unitsare interconnected within a wafer, and the wafers are interconnected ina stacked wafer construction of a memory system. The system alsoprovides an improved data storage system employing flash data storage ina stacked wafer arrangement. The vertical interconnections in a stackedwafer semiconductor device result in high density storage at arelatively low cost.

Alternative methods of fabricating the wafer scale solid state datastorage device includes using a software mapping scheme to block out thebad data storage units, with two whole wafers being placed back-to-backon a PC board. In another approach, the interconnection between wafersprovided by through-holes etched into the wafers and bundles of wiressuch as gold wires were threaded through the holes to make verticalinterconnections, thus allowing wafers to be stacked one on top of theother, producing very high packing density.

FIG. 10 shows an exemplary non-volatile data storage array used as adisk cache to enhance overall computer system performance. In thissystem, data is exchanged through an interface 800. The data is firsthandled through the non-volatile data storage devices 810 which act as acache for a mass storage device such as a hard disk drive 820. The harddisk drive 820 can provide high capacity at low cost, however, the harddrive has a slow I/O performance in comparison with the non-volatiledata storage devices 810. Thus, commonly software such as the operatingsystem components and Internet browser, word processing software,spreadsheet software, among others, can be set to permanently reside inthe caching non-volatile data storage devices 810. When these files arerequested by the laptop or desktop computer, the application can belaunched at a data rate much faster than conventional non-cached harddrives can provide. For files that are not designated to residepermanently on the cached data storage array, various caching policiescan be used to cache and replace these files. The nonvolatile memory isfaster than flash based caching devices in that to write data, there isno need to first erase and then perform a write cycle to the memorydevices.

When the nonvolatile memory devices are used as a nonvolatile cacheunit, to read data, a cache entry is retrieved based on the logicaladdress. For example, if a value of “−1” is stored in the nonvolatilecache unit, it is determined that the entry is not stored in thenonvolatile cache unit by referring to the address of the nonvolatilecache unit 810. If the corresponding entry is effective, the nonvolatilecache unit reads the data. If the data does not correspond to data to bestored in the nonvolatile cache unit, or if the data corresponds to datato be stored in the nonvolatile cache unit that was not stored in thenonvolatile cache unit, the disk mass storage unit reads the data.

If the data corresponds to data to be stored in the nonvolatile cacheunit, but has not been stored in the nonvolatile cache unit, the dataread from the disk mass storage unit can be stored in the nonvolatilecache unit. At this time, the cache entry is updated.

In the same manner as the procedure for reading data, the cache entry isretrieved based on the logical address. If the cache entry does notexist, the data is stored in the nonvolatile disk mass storage unit. Ifa corresponding cache entry exists, it is checked whether thecorresponding entry is valid. If the entry exists, data is stored in thenonvolatile cache unit. Therefore, to check whether the data has beenactually stored in the nonvolatile cache unit, data on the physicaladdress of the nonvolatile cache unit 810 is checked. For example, if avalue of “−1” is stored in the nonvolatile cache unit, it is determinedthat the entry is not stored in the nonvolatile cache unit, and thus, isnot effective and the system fetches and stores the data in thenonvolatile cache unit. First, it is checked whether an empty pageexists in the nonvolatile cache unit. If the empty page does not existin the nonvolatile cache unit, a page to be stored in the nonvolatilemass storage unit is selected from pages stored in the nonvolatile cacheunit. The page can be selected based on the frequency of input andoutput operations. Alternatively, the oldest page of the nonvolatilecache unit can be selected. The page can also be selected based on anexample of a policy for the cache. The selected page is stored in thedisk mass storage. A page address of the nonvolatile cache unit isstored in the cache entry. Additionally, data such as a time stamp maybe set. The data is stored in the nonvolatile cache unit.

In the above system, data having a high update ratio is stored in thenonvolatile cache unit to reduce the time required for data storage. Inaddition, the data stored in the cache can be maintained even if nopower is supplied.

While the preferred forms of the invention have been shown in thedrawings and described herein, the invention should not be construed aslimited to the specific forms shown and described since variations ofthe preferred forms will be apparent to those skilled in the art. Thusthe scope of the invention is defined by the following claims and theirequivalents.

1. A method for forming a high density solid state data storage system,comprising: sputtering a thin film onto a plurality of substrates,including: providing at least one target and a substrate having afilm-forming surface portion and a back portion; creating a magneticfield so that the film-forming surface portion is placed in the magneticfield with the magnetic field induced normal to the substrate surfaceportion; back-biasing the back portion of the substrate; sputteringmaterial onto the film-forming surface portion, wherein the thin formingsurface portion comprises non-volatile data storage devicesinterconnected thereto; testing a plurality of substrates; stacking theplurality of tested substrates to form the non-volatile data storagesystem, each wafer being electrically coupled to an adjacent wafer;receiving a request to store the data; and selectively storing the datain the disk storage system or caching the data in the nonvolatile datastorage devices depending on an update ratio of the data.
 2. A method asin claim 1, wherein the data is stored in the nonvolatile data storagedevices if the update ratio is greater than a threshold value.
 3. Amethod as in claim 1, wherein storing the data comprises storing dataconstituting a file allocation table (FAT) in the nonvolatile datastorage devices.
 4. A method as in claim 1, wherein storing the datafurther comprises storing information related to the storage of the datain the nonvolatile data storage devices.
 5. A method as in claim 1,comprising providing a plurality of sources to deposit materials ontothe substrate.
 6. A method as in claim 1, wherein the testing comprisesmapping and selecting only functional data storage blocks.
 7. A methodas in claim 1, comprising providing a mechanical buffer to protect thestacked substrates and housing the stacked substrates in an enclosure.8. A stacked data storage system, comprising: a plurality of testedsubstrates stacked together and having non-volatile data storage devicesformed thereon and interconnected thereto, each substrate fabricatedusing a pair of target plates placed at opposite ends of said air-tightchamber respectively so as to face each other and form a plasma regiontherebetween; a pair of magnets respectively disposed adjacent to saidtarget plates such that magnet poles of different polarities face eachother across said plasma region thereby to establish a magnetic field ofsaid plasma region between said target plates; and a substrate holderdisposed adjacent to said plasma region, said substrate holder adaptedto hold a substrate on which an alloyed thin film is to be deposited;and a back-bias power supply coupled to the substrate holder, whereindata is selectively stored in a disk drive or cached in the nonvolatiledata storage devices depending on an update ratio of the data; and anclosure covering the stacked substrates.
 9. A system as in claim 8,wherein the non-volatile data storage devices are tested, mapped andelectrically coupled in accordance with a predetermined functionality.10. A system as in claim 8, comprising a mechanical buffer to protectthe stacked substrates and an enclosure to house the stacked substrates.11. A facing targets sputtering device for semiconductor fabrication,comprising: an air-tight chamber in which an inert gas is admittable andexhaustible; a pair of target plates placed at opposite ends of saidair-tight chamber respectively so as to face each other and form aplasma region therebetween; a pair of magnets respectively disposedadjacent to said target plates such that magnet poles of differentpolarities face each other across said plasma region thereby toestablish a magnetic field of said plasma region between said targetplates; a substrate holder disposed adjacent to said plasma region, saidsubstrate holder adapted to hold a substrate on which an alloyed thinfilm is to be deposited; a back-bias power supply coupled to thesubstrate holder; wherein the substrate includes an array of datastorage devices formed thereon; and an automated assembly machine tostack a plurality of tested substrates to form a non-volatile datastorage device, wherein data is selectively stored in a disk drive orcached in the nonvolatile data storage devices depending on an updateratio of the data.
 12. A facing targets sputtering device according toclaim 11, comprising a first target power supply coupled to one of thetarget plates and wherein the first target power supply is a DC or an ACelectric power source.
 13. A facing targets sputtering device accordingto claim 11, comprising a second target power supply coupled to theremaining target plate, wherein the first and second target powersupplies comprises DC and AC electric power sources.
 14. A facingtargets sputtering device according to claim 11, wherein the automatedassembly machine comprises a robot arm to move the wafer.
 15. A facingtargets sputtering device according to claim 11, comprising a magnetroncoupled to the chamber.
 16. A facing targets sputtering device accordingto claim 11, comprising a chuck heater mounted above the wafer.
 17. Afacing targets sputtering device according to claim 11, comprising amemory tester to characterize the data storage devices
 18. A facingtargets sputtering device according to claim 11, comprising wire-bondingequipment to electrically connect the substrates.
 19. A facing targetssputtering device according to claim 11, wherein the data storagedevices comprise row and column decoders.
 20. A facing targetssputtering device according to claim 11 wherein each data storage devicecomprise an address input and a data input/output.